56 lines
946 B
C
56 lines
946 B
C
#ifndef EMU_CPU_CONST_H
|
|
#define EMU_CPU_CONST_H
|
|
|
|
typedef enum
|
|
{
|
|
HLT = 0x00,
|
|
ADD = 0x01,
|
|
SUB = 0x02,
|
|
MUL = 0x03,
|
|
DIV = 0x04,
|
|
LBS = 0x05,
|
|
RBS = 0x06,
|
|
BAN = 0x07,
|
|
BOR = 0x08,
|
|
BXO = 0x09,
|
|
BNO = 0x0A,
|
|
PUS = 0x0B,
|
|
POP = 0x0C,
|
|
JMP = 0x0D,
|
|
JEQ = 0x0E,
|
|
JNZ = 0x0F,
|
|
CAL = 0x10,
|
|
RET = 0x11,
|
|
REG = 0x12,
|
|
INT = 0x13,
|
|
INP = 0x14,
|
|
OUT = 0x15,
|
|
DIN = 0x16,
|
|
DOT = 0x17,
|
|
MOV = 0x18
|
|
} CpuInstructions;
|
|
|
|
typedef enum
|
|
{
|
|
R0 = 0x0,
|
|
R1 = 0x1,
|
|
R2 = 0x2,
|
|
R3 = 0x3,
|
|
ACU = 0x4,
|
|
PC = 0x5,
|
|
SP = 0x6
|
|
} CpuRegisters;
|
|
|
|
typedef enum
|
|
{
|
|
value = 0x0,
|
|
register = 0x1,
|
|
ram = 0x2,
|
|
pointerInRegister = 0x3
|
|
} ArgumentInfo;
|
|
|
|
#define INSTRUCTION_BIT_MASK 0b1111111111110000
|
|
#define INSTRUCTION_ARG_1_INFO_MASK 0b0000000000001100
|
|
#define INSTRUCTION_ARG_2_INFO_MASK 0b0000000000000011
|
|
|
|
#endif |